Junction Field-Effect Transistors (JFETs) are made in active areas in semiconductor substrates where the active area is surrounded by field oxide. In the active area, a conductive area called a well is formed and that well forms a PN junction with the bulk substrate. That PN junction is called the back gate, and it is conventional to form a surface contact to the well so that bias can be applied to the well region for various purposes. This separate contact for the well consumes chip area and reduces the overall total number of devices that can be formed on any wafer.
In the well, a conductive channel region is formed, and in that channel region, conductive source, drain and gate regions are formed. These source, drain and gate regions form PN junctions with the channel region. In a new class of processes and structures which are the subject of patent applications previously filed by the assignee of the present invention, these source, drain and gate regions are very shallow. Each of the source, drain and gate regions has a surface contact.
The JFET functions to selectively switch current flow between the source and drain contacts. This is done by applying suitable voltages to the source and drain and applying a bias voltage to the gate contact which is such as to cause pinchoff when no current flow is desired and to open the channel when current flow is desired. Pinchoff is a condition where depletion regions from the gate-channel junction and the channel substrate junction meet and block current flow for lack of minority carriers in the channel. In an n-channel enhancement-mode JFET, current flows when the gate is biased to a positive voltage which is sufficient to cause the depletion regions to not meet, thereby opening the channel for conduction. Pinchoff is achieved by holding the gate at ground or a negative voltage Depletion-mode devices are also available which are normally conductive when a source-to-drain bias is applied and the gate voltage is below the pinchoff voltage. In these devices, the gate must be driven to a voltage adequate to cause pinchoff to cut off current flow.
All these devices require proper operation of the shallow PN gate-channel junction to operate as designed. If this junction is shorted, the device does not operate as a normal four terminal JFET.
In making JFETS, a class of processes exist in which a layer of silicon dioxide is deposited over the entire structure including the active area. Openings are etched in this oxide layer where the source, drain and gate and back gate surface contacts are to be formed. This layer is thin however, and the openings are etched with a process that can over-etch and eat away the field oxide at the edge of the active area so as to expose the sidewall of the active area. If the over etching is bad enough, the gate-channel, source-channel and drain-channel PN junctions can be exposed. Then when conductive polycrystalline silicon (hereafter polysilicon) or metal is deposited into the openings to form the surface contacts, the gate-channel, source-channel and drain-channel PN junctions can be shorted. This can render the device inoperative, but it can also be used to advantage to eliminate the surface contact for the back gate.